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NMI/IRQ and cycle delays

NMI/IRQ and cycle delays
by on (#94951)
Has anyone been able to accurately determine the actual number of cycles that passes when an NMI or IRQ is encountered? Quoting WDC in Chapter 13 (page 200):

At either seven or eight cycles per interrupt – the time required to stack the program counter, pc bank, and status register, and then jump through the interrupt vectors – the interrupt response cycle is among the longest-executing 65x instructions. Since an interrupt always lets the current instruction complete execution, there is a possible seven-cycle delay between the receipt of an interrupt and the servicing of one; this delay is called the interrupt latency. Small as the delay is, it can be significant in the servicing of data acquisition and control devices operating in real time, systems in which it is important that interrupts be disabled as little as possible.

Naturally the part about pushing PC bank is 65816 specific thus doesn't apply to the 6502, but the rest does. I'm wondering folks here know the exact number of cycles that passes after the last (non-interrupt) CPU instruction executes and control is handed over to the NMI routine.

by on (#94969)
It's 7 cycles. This page has some relevant visual 6502 tests for special cases, interesting stuff.