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MDC5

MDC5
by on (#43140)
I notice EWROM have some compatibly with RAM/ROM mapping for Disksystem Adapter. I hacked Disksystem Bios for MMC5, replaced Program ROM, exchaged Charcter ROM to RAM. Iceclimber diskversion (FMC-ICD) worked on MMC5.
Another game is worked (CLD, ICE, TC1 + TC2, VBW, AKM)! I named this attempt 'MDC5' (Multi Diskimage Control for mmc5).

The problem is that interchangeability is not complete. My attempt is inferior compared with Power Pak and FDS loader. I think it is technically interesting. I want someone to cooperate in development because it takes time.

I want upload some stuff, but I don't know best upload space....
Problem list
by on (#43141)
- Extra Sound
This problem cannot be evaded. I choose that games does not use extra sound.

- Save file system
It needs more Program RAM area, I have to find Program RAM extra address A15-A16.

- Patch system
To control scroll mirroring, timer interrupt and swapped disk, Games read and write $402x and $403x without BIOS. It must be patch for MMC5 control registers.

- .fds to .nes converter
4M bit ROM can include 7 (or 8) diskside. The latest converter can concat FDSs and make NES header. It cannot link Patch system and disk mapping infomation. I write assemblely source, and have linked by hand power.

by on (#43279)
I uploaded MDC5 stuff. This file is deleted within 24 hours.
http://www.megaupload.com/?d=S8U41FSA

The problem of the capacity of RAM was solved. ETROM have two RAM space. W-RAM-0 and W-RAM-1 can use each 0x8000 byte RAM. I found undocumented RAM mapping for MMC5.

W-RAM-0:
mappable $6000-, $8000-, $a000- and $c000-$dfff. data is battery-backuped.

W-RAM-1:
mappable $6000 only. It is not connected with the battery.

by on (#43286)
Where did you find this "undoccumented" info ? How accurate is it ?
I see on the boards that with the correct uses of solder pads, either chip can be battery backuped and not battery backuped at will. The default config is W-RAM-0 with battery and W-RAM-1 with battery, but can be changed.

by on (#43304)
After having seen your reference, I wrote the test program for RAM bank switch. My reference was a mistake.

W-RAM-0 and W-RAM-1 can map $6000-, $8000-, $a000-, $c000-$dfff. When only $5113 of "Select PRG RAM chip bit" was effective, I misunderstood it.
I did not notice that the battery backup can config. sorry.
Re: MDC5
by on (#130618)
Great work!
Can you share your client applications?
Re: MDC5
by on (#130619)
I've played with the idea myself, converting FDS-games to NES (someone obviously did it with "Doki Doki Panic" earlier, however I think the save-feature was broken). The showstopper for me to try and do this kind of hacking was 1) MMC5-documentation is not really for mortals like myself , 2) I am not sure how easy/cheap it is for people to put this stuff on reproduction (MMC5) cartridges?

Someone should create a less complex mapper that allows for easier FDS->NES conversion. :)
Re: MDC5
by on (#130621)
oRBIT2002 wrote:
I've played with the idea myself, converting FDS-games to NES (someone obviously did it with "Doki Doki Panic" earlier, however I think the save-feature was broken). The showstopper for me to try and do this kind of hacking was 1) MMC5-documentation is not really for mortals like myself , 2) I am not sure how easy/cheap it is for people to put this stuff on reproduction (MMC5) cartridges?

Someone should create a less complex mapper that allows for easier FDS->NES conversion. :)


MMC5 cartridge is cheap , Just about $2.
Re: MDC5
by on (#130622)
You could try targeting mapper 40, 50, or NROM-368.

MMC5 carts to repurpose are fairly hard to come across ... at least where I am; the local retro/import gaming shop has only a few, all famicom imports, ranging from $8 up to $20.
Re: MDC5
by on (#130623)
lidnariq wrote:
You could try targeting mapper 40, 50, or NROM-368.

MMC5 carts to repurpose are fairly hard to come across ... at least where I am; the local retro/import gaming shop has only a few, all famicom imports, ranging from $8 up to $20.


How to make a mapper 40/50 cardridge?
Re: MDC5
by on (#130625)
byemu wrote:
How to make a mapper 40/50 cardridge?
It should fit neatly into a PAL16R4, or at least a 22V10.

Otherwise, looks like 7 logic ICs: 74'00, 74'157, 74'138, 74'161, 74'86, 74'32, and a GD4020:
http://img.photobucket.com/albums/v129/ ... d1d440.jpg
I tentatively think that one's mapper 50.

Bootgod received a picture of a cart that I'm guessing is mapper 40? It's got 8 logic ICs: 74'138, two 74'74, 74'04, 74'139, 74'11, TC4020, and a TC4075. (Also four ROMs...?)
Re: MDC5
by on (#130626)
lidnariq wrote:
byemu wrote:
How to make a mapper 40/50 cardridge?
It should fit neatly into a PAL16R4, or at least a 22V10.

Otherwise, looks like 7 logic ICs: 74'00, 74'157, 74'138, 74'161, 74'86, 74'32, and a GD4020:
http://img.photobucket.com/albums/v129/ ... d1d440.jpg
I tentatively think that one's mapper 50.

Bootgod received a picture of a cart that I'm guessing is mapper 40? It's got 8 logic ICs: 74'138, two 74'74, 74'04, 74'139, 74'11, TC4020, and a TC4075. (Also four ROMs...?)


I'm interested in PAL16R4's alternative 7 logic ICs.
Appreciate further details.
Re: MDC5
by on (#130660)
Best I can figure to make mapper 40, without actually sitting down and writing some VHDL:

The four latch pins of the 16R4 would contain Q2 through Q0, and CD4020-Reset. (The first three are N/C for internal feedback paths; the last goes to a CD4020's RESET pin. The CD4020's Q13 pin is connected through a resistor to the base of a BJT that will in turn pull CPU /IRQ down at the right time.
Three non-registered outputs go to PRG A13 through A15, and are multiplexed between Q2 through Q0 and CPU /A15 through A13. The last non-registered output would produce /ROMOE to both map it from $6000-$FFFF and to prevent bus conflicts.

The eight general-purpose inputs would be connected to CPU D0, D1, D2, M2, /ROMSEL=/A15, A14, A13, R/W. PAL16R4 /OE is connected to ground. CPU M2 is additionally connected through a small RC to PAL16R4 CLK (because /ROMSEL needs to be stable before it can be latched).

Total: PAL16R4, CD4020, 2N2222 (or similar), two 1kΩ resistors, one ≈68pF capacitor.
Re: MDC5
by on (#130782)
lidnariq wrote:
Best I can figure to make mapper 40, without actually sitting down and writing some VHDL:

The four latch pins of the 16R4 would contain Q2 through Q0, and CD4020-Reset. (The first three are N/C for internal feedback paths; the last goes to a CD4020's RESET pin. The CD4020's Q13 pin is connected through a resistor to the base of a BJT that will in turn pull CPU /IRQ down at the right time.
Three non-registered outputs go to PRG A13 through A15, and are multiplexed between Q2 through Q0 and CPU /A15 through A13. The last non-registered output would produce /ROMOE to both map it from $6000-$FFFF and to prevent bus conflicts.

The eight general-purpose inputs would be connected to CPU D0, D1, D2, M2, /ROMSEL=/A15, A14, A13, R/W. PAL16R4 /OE is connected to ground. CPU M2 is additionally connected through a small RC to PAL16R4 CLK (because /ROMSEL needs to be stable before it can be latched).

Total: PAL16R4, CD4020, 2N2222 (or similar), two 1kΩ resistors, one ≈68pF capacitor.

Thanks