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MMC1 behavior on a bit7 high set (reset shift reigster)

MMC1 behavior on a bit7 high set (reset shift reigster)
by on (#123587)
I have a question about what behavior real MMC1 mapper hardware (iNES mapper 001) has when PRG-ROM is written with bit 7 set to reset the 5bit shift register in this mapper. According to "Disch's original notes" at http://wiki.nesdev.com/w/index.php/INES_Mapper_001, when doing a reset "bits 2,3 of reg $8000 are set (16k PRG mode, $8000 swappable)". This is indeed the behavior I observe in FCEUX 2.2.2.

However, the other two documents I could find about the MMC1 mapper make no mention of this behavior where the shift register reset also resets part of the $8000 control register:
http://wiki.nesdev.com/w/index.php/MMC1
http://nocash.emubase.de/everynes.htm#mapper1mmc1prg32k16kvrom8k4knt

Testing with the Nintendulator emulator, I observe the latter behavior where a reset doesn't affect $8000 or do any bank switching on its own.

Does anyone have more information about this particular behavior? Or maybe someone with real hardware could verify which of these two behaviors is correct? Thanks.
Re: MMC1 behavior on a bit7 high set (reset shift reigster)
by on (#123588)
I know I've needed to know the effect of it in the past and my note on this sounds reliable:

Writing byte with high bit set resets shift register and also sets bits 2 and 3 of $8000, enabling 16K PRG bank at $8000. No other register bits are affected.
Re: MMC1 behavior on a bit7 high set (reset shift reigster)
by on (#123597)
From MMC1:
"1: Reset shift register and write Control with (Control OR $0C), locking PRG ROM at $C000-$FFFF to the last bank."